A high-speed digital data stream can be transmitted through a transmission line to a receiver without an accompanying clock signal. A clock and data recovery (CDR) circuit in the receiver generates one or more clock signals from an approximate frequency reference signal, and then phase-aligns the clock signals to the transitions in the data stream. The receiver uses the clock signals to sample bits in the data stream.
Peripheral Component Interconnect Express (PCI-E) is a computer expansion card standard for personal computers. PCI-E 1.0 supports a data rate of 2.5 gigabits per second (Gbps). PCI-E 2.0 supports a data rate of 5 Gbps. The data rate of a data signal indicates a number of bit periods in the data signal per unit of time. A transmitter initially begins transmitting a data signal to a receiver at the PCI-E 1.0 data rate of 2.5 Gbps. Subsequently, the transmitter and receiver attempt to increase the data rate to 5 Gbps based on the PCI-E 2.0 standard to reduce power consumption and to increase the performance of the transmission system. The CDR circuit in the receiver provides a corresponding increase in the frequencies of the clock signals based on the increase in the data rate.
FIG. 1 illustrates an example of a prior art clock and data recovery (CDR) circuit 100 that can adjust the frequencies of clock signals in response to a change in the data rate of a received data signal. CDR circuit 100 includes a phase frequency detector (PFD) circuit 101, multiplexer circuits 102, charge pump circuit 104, low pass filter (LPF) circuit 105, voltage-controlled oscillator (VCO) circuit 106, L counter circuit 107, M counter circuit 108, counter circuit 109, multiplexer circuits 110, phase detector (PD) circuit 111, N counter circuit 112, and lock detector circuit 114.
N counter circuit 112 divides the frequency of a reference clock signal REFCLK to generate a periodic frequency divided clock signal RCKD. Clock signal RCKD is provided to an input of phase frequency detector circuit 101. A clock signal can be any type of periodic signal.
Phase frequency detector (PFD) 101 compares the phase and the frequency of clock signal RCKD to the phase and the frequency of a periodic feedback clock signal FBCLK to generate error signals UPPF and DNPF. Error signals UPPF and DNPF are indicative of the differences between the phases and the frequencies of clock signals RCKD and FBCLK. Multiplexers 102 include two 2-to-1 multiplexers. Initially, multiplexers 102 are configured to provide error signals UPPF and DNPF to charge pump 104 as error signals UP and DN, respectively.
Charge pump 104 converts the UP and DN error signals into an analog control voltage VCL. The control voltage VCL is provided to a control input of VCO 106. Low pass filter 105 attenuates high frequency components of the control voltage VCL.
VCO 106 generates 4 periodic output clock signals VCO[3:0]. VCO 106 adjusts the phases and frequencies of clock signals VCO[3:0] in response to changes in control voltage VCL. The output clock signals VCO[3:0] are transmitted to inputs of L counter circuit 107. L counter circuit 107 divides the frequencies of clock signals VCO[3:0] by a frequency division value to generate 4 periodic clock signals CLKL[3:0]. The frequency division value of L counter circuit 107 is set to divide by 1, 2, 4 or 8. M counter circuit 108 divides the frequency of one of clock signals CLKL[3:0] by a frequency division value to generate feedback clock signal FBCLK. The frequency division value of M counter circuit 108 is set to divide by 1, 4, 5, 8, 10, 16, 20, or 25.
PFD 101, multiplexers 102, charge pump 104, low pass filter 105, VCO 106, and counters 107-108 form a phase-locked loop (PLL) that adjusts the phase and frequency of clock signal FBCLK to cause the phase and frequency of FBCLK to match the phase and frequency of clock signal RCKD. Lock detector circuit 114 asserts the Lock signal in response to error signals UPPF and DNPF indicating that clock signals RCKD and FBCLK are aligned in phase and have the same frequency in a lock state.
The clock signals CLKL[3:0] generated by L counter 107 are provided to inputs of multiplexers 110 and to inputs of counter circuit 109. Counter circuit 109 divides the frequencies of clock signals CLKL[3:0] by 2 to generate the frequencies of 4 periodic clock signals CLKC[3:0] at additional inputs of multiplexers 110. Multiplexers 110 are initially configured to provide the output clock signals CLKC[3:0] of counter 109 to inputs of PD 111 as 4 periodic feedback clock signals CLKOUT[3:0].
Phase detector (PD) 111 compares the phase of the differential input data signal DXP/DXN to the phases of feedback clock signals CLKOUT[3:0]. The 4 clock signals CLKOUT[3:0] have relative phases of 0°, 90°, 180°, and 270°. PD 111 generates error signals UPPD and DNPD that are indicative of the differences between the phase of the differential input data signal DXP/DXN and the phases of clock signals CLKOUT[3:0].
Error signals UPPD and DNPD are transmitted to inputs of multiplexers 102. After the Lock signal has been asserted, multiplexers 102 are reconfigured to provide the output error signals UPPD and DNPD of phase detector 111 to charge pump 104 as error signals UP and DN, respectively. CDR circuit 100 then adjusts the phases of feedback clock signals CLKOUT[3:0] in response to changes in the phase of input data signal DXP/DXN.
The data rate of the input data signal DXP/DXN doubles when changing from PCI-E 1.0 to PCI-E 2.0. Multiplexers 110 are then reconfigured by a control signal SW to provide clock signals CLKL[3:0] to inputs of PD 111 as the 4 feedback clock signals CLKOUT[3:0]. As a result, the frequencies of clock signals CLKOUT[3:0] increase to 2 times their initial frequencies, but the frequencies of the output clock signals VCO[3:0] of VCO 106 remain the same. The PLL in CDR circuit 100 remains in the lock state after the data rate of the input data signal DXP/DXN doubles. Clock signals CLKOUT[3:0] are also provided to a deserializer circuit.